Method for manufacturing iii-v compound semiconductor device

ABSTRACT

In a method for manufacturing a III-V compound semiconductor device in which a second conductivity type impurity is selectively diffused into part of one main plane of a first conductivity type III-V compound semiconductor crystal, thereby forming a thin diffusion layer, the improvement is characterized in that an Al2O3 film is first formed on the main plane, part of the Al2O3 film corresponding to the area on the semiconductor crystal where the impurity is diffused is removed by etching, a SiO2 film is formed on the Al2O3 film and on the main plane of the compound semiconductor crystal in the area exposed by etching, part of the SiO2 film in direct contact with the main plane of the compound semiconductor crystal is etched, thereby exposing part of the main plane of the semiconductor crystal, and the second conductivity type impurity is diffused through the exposed part of the semiconductor crystal whereby the second conductivity type thin diffusion layer is formed spreading substantially over the whole of such part of said compound semiconductor as has direct contact with said SiO2 film.

METHOD FOR MANUFACTURING III-V COMPOUND SEMICONDUCTOR DEVICE Inventors:Eiichi Adachi, Mitaka; Kazutoshi Saito, Hachioji, both of JapanAssignee: Hitachi, Ltd., Tokyo, Japan Filed: Jan. 24, 1972 Appl.,No.:220,177

[30] Foreign Application Priority Data Jan. 22, 1971 Japan 46-1582 [52]US. Cl. 148/187, 148/186, 148/189, 29/576 [51] Int. Cl. H011 7/34 [58]Field of Search 148/189, 187; 29/576 [56] References Cited UNITED STATESPATENTS 3,629,018 12/1971 Henderson et al 148/187 3,698,071 10/1972 Hall148/186 X 3,602,984 9/1971 Trent 148/187 X 3,298,879 1/1967 Scott et al148/189 X 3,697,334 lO/l972 Yamamoto et al. 148/188 X 3,615,941 10/1971Yamada et al 148/187 Apr. 30, 1974 Primary Examiner-G. T. OzakiAttorney, Agent, or Firm-Craig and Antonelli [57] ABSTRACT In a methodfor manufacturing a III-V compound semiconductor device in which asecond conductivity type impurity is selectively diffused into part ofone main plane of a first conductivity type Ill-V compound semiconductorcrystal, thereby forming a thin diffusion layer, the improvement ischaracterized in that an A1 0 film is first formed on the main plane,part of the A1 0 film corresponding to the area on the semiconductorcrystal where the impurity is diffused is removed by etching, a SiO filmis formed on the A1 0 film and on the main plane of the compoundsemiconductor crystal in the area exposed by etching, part of the SiO,film in direct contact with the main plane of the compound semiconductorcrystal is etched, thereby exposing part of the main plane of thesemiconductor crystal, and the second conductivity type impurity isdiffused through the exposed part of the semiconductor crystal wherebythe second conductivity type thin diffusion layer is formed spreadingsubstantially over the whole of such part of said compound semiconductoras has direct contact with said SiO film.

7 Claims, 7 Drawing Figures BACKGROUND OF THE INVENTION This inventionrelates to a method for selectively diffusing an impurity into a III-Vcompound semiconductor.

DESCRIPTION OF THE PRIOR ART to a depth smaller than 1.5a, with a highreproducibility. Furthermore, the prior art method gave rise to theproblem that when the diffusion depth was shallow, a heavy metal wasdiffused into the semiconductor crystal in the electrode formingprocess, to result in degrading the characteristic of the junctiondirectly beneath the electrode.

SUMMARY OF THE INVENTION A general object of this invention is toprovide a method for selectively diffusing an impurity into a IIIVcompound semiconductor free of prior art problems.

Briefly, the method of this invention is characterized in that a III-Vcompound semiconductor crystal is coated with an A1 film, part of thefilm located on the area of the crystal into which an impurity isdiffused is removed by etching, a SiO film is deposited on the removedarea, part of the SiO film in contact with the semiconductor crystal isetched, thereby exposing part of said semiconductor crystal, and theimpurity is diffused thereinto through the exposed part of the crystal.According to this method, the junction formed directly beneath theexposed part of the semiconductor crystal can be made deep enough, andmost of the other part can be formed into a shallow junction. Hence, ifelectrodes are formed in the exposedpart of the semiconductor crystal,the foregoing prior art problems can be solved.

More specifically, according to this invention, it has beenexperimentally discovered that when an impurity is diffused thereintothrough a window on the SiO film formed on the III-V compoundsemiconductor crystal,

a diffusion layer being very thin compared with they depth of thediffusion in the direction perpendicular to the boundary-in the windowportion between the Si0 film and the compound semiconductor crystal isspread anomalously in parallel with the boundary. Such spreadingphenomenon occurs more conspicuously as the diffusion temperatureincreases and the diffusion time becomes longer. For example, when zincis diffused into a GaAs P crystal at 750 C for about 4 hours, thediffusion depth directly beneath the window disposed on the SiO film is3;, the depth of the shallow diffusion part is 111., and its spread is130p. This phenomenon is caused by Ga atoms in the compoundsemiconductor being diffused into SiO through the boundary, therebyforming vacancies of Ga, and anomalously rapid diffusion takes placethrough the vacancies. When an Al o film or the like is deposited on thecompound semiconductor, the possibility of this phenomenon is relativelysmall. This is thought to occur because the diffusion coefficient of Gainto A1 0 is smaller than that of Ga into SiO Therefore, when an SiOfilm is deposited on the part where an impurity is diffused and an AI Ofilm is deposited directly on the compound semiconductor in the areaother than said diffusion part, it becomes possible to form a shallowdiffusion layer only in the region directly beneath the SiO film. Inother words, a relatively deep diffusion layer is formed in the areawhere neither the SiO film nor the A1 0 film is deposited. Therefore, inthe electrode forming process, there are no possibilities ofdeteriorating the characteristics at the junction directly beneath theelectrode.

According to-this invention, a silicate glass including a III group or Vgroup element, such as SiO (P 0 and SiO (B 0 may be used instead of SiOAccording to one aspect of the present invention for realizing itsmethod, a compound semiconductor crystal is heated and, while heating,an A1 0 film is formed on one main plane of said crystal and then thepart of this film corresponding to the area where an impurity isdiffused is removed by etching, an SiO film is formed on the A1 0 film,an etching window, whose area is smaller than the place where animpurity is diffused, is formed in the part of said SiO film in directcontact with said crystal, and the impurity is diffused thereintothrough said window. The selective diffusion mask formed in the aboveprocess can be utilized as a passivation film for the semiconductordevice.

The method of this invention is highly useful not only for GaAs but alsofor compound semiconductors having the composition GaAs,,P, (where 0.5 Ex g l and Ga Al As (whereO x 0.6). When the ratio of GaP in the mixedcrystal GaAs P is large, the temperature for impurity diffusion must beincreased. This temperature, for example, is about 800 to 900 C. At suchhigh temperatures, however, it is impossible to realize desirableimpurity diffusion even if M 0 is used for the diffusion mask. Themaximum temperature at which A1 0 is used for the diffusion mask isabout 750 C for GaAs P The same consideration is necessary as to themixed crystal Ga -Al As (where 0.6 5 x g I).

If the diffusion temperature is below about 600 C, a long time isrequired to obtain the necessary depth of diffusion junction directlybelow the electrode. For example, it takes about 36 hours for a 2p. deepdiffusion junction when zinc is diffused into GaAs P (x =0.4) at about600 C.

Features and advantages of this invention will be more apparent from thefollowing specification of one illustrative embodiment in-conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a diagram showing a deviceused for carrying out the method of this invention, and

FIGS. 2a through 2f are diagrams illustrating the steps of the method ofthis invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Described below is oneembodiment of this invention wherein a diffusion mask is formed on acompound semiconductor GaAsP substrate by using a device for forming aselective diffusionmask making device as shown in FIG. 1.

In FIG. 1, the reference numeral 11 denotes an ntype GaAsP mixed crystalsubstrate having a specific resistance of Q-cm, 12 a quartz glass belljar, 13 a pipe through which SiH. gas is introduced into the bell jar,14 a pipe through which 0 and N gases are introduced thereinto, 15 areservoir of an aluminum compound such as tri-iso-butyl aluminum ortriethoxyaluminum, 16 a pipe for introducing thereinto N gas which isused as the carrier of the aluminum compound, 17 a heating device, and18 a switch cock.

FIGS. 2a through 2f illustrate the production steps of the methodaccording to this invention. An n-type GaAs P (where 0.5 g x E l)substrate 11 is heated to a temperature of about 300 to about 500 C and,while heating, N gas and aluminum compound vapor are supplied to thesubstrate 11, these gases are reacted by 0 gas, whereby an A1 0 film 21is deposited on the GaAsP substrate. Practically, the necessarythickness of the M 0 film is about 1,000A, for example. To obtain this,it is necessary to carry out the reaction at about 400 C for about 15minutes. A window is disposed in the necessary part of the M 0 film 21by a known photoetching method, as shown in FIG. 2b. The GaAsP substrate11 is heated to a temperature of about 300 to about 500 C, SiH gas and Ngas are supplied thereto to react with 0 gas, whereby an SiO film 22 isdeposited on the substrate 11, as shown in FIG. 20. The practicallynecessary thickness of the SiO film is about 6,000A. As shown in FIG.2d, a window is disposed in the necessary part of the SiO film 22 by aknown photoetching method. The resultant sample is taken out of thedevice as in FIG. 1 and placed together with 5mg of ZnAs in a quartztube and sealed, and then it is heated at about 750 C for about 4 hours.By this process, as shown in FIG. 2e, a 3p. thick diffusion layer 23whose conductivity type is opposite to that of the substrate is formeddirectly beneath the window disposed on the SiO film, and a 0.5 to lg.thick diffusion layer 23 is formed beneath the window disposed on the A10 film. Aluminum is deposited by evaporation on the SiO film throughsaid window, and an Au lead wire is bonded to this aluminum layer andused as electrode 24, for the diffusion layer 23. An Au-Ge alloy isbonded to the bottom of the GaAsP substrate and is usedas an electrode25 on the side of substrate. Thus, a diode as shown in FIG. 2f isobtained.

When the diode is forward-biased, light emission occurs in the windowportion disposed on the A1 0 film 21. Because the diode formed in theabove manner has a shallow diffusion layer, its external quantumefficiency of light emission is greater than that of the diodeobtainable by using a double layer A1 0 and Si0 (P 0 as a diffusionmask, according to the prior art. Also, according to the invention, theSiO film which covers most of the junction surface is heat-treated atthe diffusion temperature and, hence it is fine-grained and highlyresistant against moisture.

In the above embodiment, a silicate glass including a ll] group or Vgroup element such as SiO (P 0 and SiO (B 0 may be used in place of SiOAlso, according to the invention, an n-type impurity may be diffusedinto a p-type GaAsP mixed crystal substrate, or GaAlAs or GaAs may beused instead of GaAsP.

While one specific embodiment of the invention and particularmodifications thereof has been illustrated and described in detail, itis particularly understood that the invention is not limited or thereby.

We claim:

1. A method for manufacturing a lIl-V compound semiconductor device,comprising the following steps:

a. forming an A1 0 film on a principal plane of a first conductivitytype III-V compound semiconductor substrate;

b. removing a portion of said AI O film corresponding to the part ofsaid semiconductor crystal where an impurity is to be diffused, said AlO film being formed by thermal decomposition of an organic compoundselected from the group consisting of tri-iso-butyl aluminum andtriethoxy-aluminum at a temperature of about 300 to about 500 C;

c. forming a silicate glass film on said Al O film and on the principalplane of said compound semiconductor substrate in the part exposed instep (b), the thickness of said silicate glass film being about 6,000 A;

d. removing a portion of said silicate glass film in direct contact withthe principal plane of said compound semiconductor substrate so that thepart of said principal plane corresponding to said portion is exposed;

e. diffusing a second conductivity type impurity whose conductivity typeis opposite to said first conductivity type into said substrate throughsaid exposed part of the principal plane in the range of temperaturebetween 600 and 750 C., whereby a second conductivity type diffusionlayer is formed, said second conductivity type diffusion layer beingspread substantially over the part of the compound semiconductor indirect contact with said silicate glass film;

f. disposing an electrode for said second conductivity type layer insaid window; and

g. disposing an electrode for said first conductivity type layer in saidfirst conductivity type semiconductor substrate.

2. A method for manufacturing a Ill-V compound semiconductor device inaccordance with claim 1, in

which said III-V compound semiconductor substrate is selected from amongthe group consisting of GaAs P (where 0.5 5 x g l) and Ga, ,Al,As

(where 0 E x g 0.6).

3. A method for manufacturing a III-V compound semiconductor device inaccordance with claim 2, wherein said step (e) is carried out until thedepth of said second conductivity type diffusion layer beneath saidsilicate glass film is between 0.5 and 1 micron.

4. A method for manufacturing a III-V compound semiconductor device inaccordance with claim 1, in which said silicate glass contains anelement selected from the group consisting of III group elements and Vgroup elements.

5. A method for manufacturing a III-V compound semiconductor device inaccordance with claim 1, in which said silicate glass is selected fromthe group consisting of SiO SiO (P 0 and SiO;, (B 0 6. A method formanufacturing a III-V compound semiconductor device in accordance withclaim 1, in which said silicate glass is made of SiO 7. A method formanufacturing a III-V compound semiconductor device in accordance withclaim I, wherein said step (g) comprises forming said electrode on theside of said substrate opposite said principal plane.

2. A method for manufacturing a III-V compound semiconductor device in accordance with claim 1, in which said III-V compound semiconductor substrate is selected from among the group consisting of GaAsxP1 x (where 0.5 < or = x < or = 1) and Ga1 xAlxAs (where 0 < or = x < or = 0.6).
 3. A method for manufacturing a III-V compound semiconductor device in accordance with claim 2, wherein said step (e) is carried out until the depth of said second conductivity type diffusion layer beneath said silicate glass film is between 0.5 and 1 micron.
 4. A method for manufacturing a III-V compound semiconductor device in accordance with claim 1, in which said silicate glass contains an element selected from The group consisting of III group elements and V group elements.
 5. A method for manufacturing a III-V compound semiconductor device in accordance with claim 1, in which said silicate glass is selected from the group consisting of SiO2, SiO2 (P2O5) and SiO2 (B2O3).
 6. A method for manufacturing a III-V compound semiconductor device in accordance with claim 1, in which said silicate glass is made of SiO2.
 7. A method for manufacturing a III-V compound semiconductor device in accordance with claim 1, wherein said step (g) comprises forming said electrode on the side of said substrate opposite said principal plane. 